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1 ? fn9290.4 isl6312a four-phase buck pwm controller with integrated mosfet dr ivers for intel vr10, vr11, and amd applications the isl6312a four-phase pwm control ic provides a precision voltage regulation system for advanced microprocessors. the integration of power mosfet drivers into the controller ic marks a departure from the separate pwm controller and driver c onfiguration of previous multiphase product families. by reducing the number of external parts, this integrati on is optimized for a cost and space saving power management solution. one outstanding feature of this controller ic is its multi-processor compatibility, allowing it to work with both intel and amd microprocessors. included are programmable vid codes for intel vr10, vr11, as well as amd dac tables. a unity gain, different ial amplifier is provided for remote voltage sensing, compensating for any potential difference between remote and local grounds. the output voltage can also be positively or negatively offset through the use of a single external resistor. the isl6312a also includes adv anced control loop features for optimal transient response to load apply and removal. one of these features is highly accurate, fully differential, continuous dcr current sensin g for load line programming and channel current balance. active pulse positioning (app) modulation is another unique feature, allowing for quicker initial response to high di/dt load transients. this controller also allows the user the flexibility to choose between phase detect or lgat e detect adaptive dead time schemes. this ability allows the isl6312a to be used in a multitude of applications wher e either scheme is required. protection features of this c ontroller ic include a set of sophisticated overvoltage, un dervoltage, and overcurrent protection. furthermore, the isl6312a includes protection against an open circuit on the remote sensing inputs. combined, these features prov ide advanced protection for the microprocessor and power system. features ? integrated multiphase power conversion - 2-phase or 3-phase operation with internal drivers - 4-phase operation with external pwm driver signal ? precision core voltage regulation - differential remote voltage sensing - 0.5% system accuracy over-temperature - adjustable reference-voltage offset ? optimal transient response - active pulse positioning (app) modulation - adaptive phase alignment (apa) ? fully differential, continuous dcr current sensing - accurate load line programming - precision channel current balancing ? user selectable adaptive dead time scheme - phase detect or lgate detect for application flexibility ? variable gate drive bias: 5v to 12v ? multi-processor compatible - intel vr10 and vr11 modes of operation - amd mode of operation ? microprocessor voltag e identification inputs -8-bit dac - selectable between intel?s extended vr10, vr11, amd 5-bit, and amd 6-bit dac tables - dynamic vid technology ? overcurrent protection ? load current indicator ? multi-tiered overvoltage protection ? digital soft-start ? selectable operation frequency up to 1.5mhz per phase ? pb-free (rohs compliant) ordering information part number (note) part marking temp. (c) package (pb-free) pkg. dwg. # ISL6312ACRZ* isl6312 acrz 0 to +70 48 ld 7x7 qfn l48.7x7 isl6312airz* isl6312 airz -40 to +85 48 ld 7x7 qfn l48.7x7 note: these intersil pb-free pl astic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal ( e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. *add ?-t? suffix for tape and reel. please refer to tb347 for details on reel specifications. data sheet caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006, 2007, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. april 29, 2010
2 fn9290.4 april 29, 2010 pinout isl6312a (48 ld qfn) top view isl6312a integrated dr iver block diagram vid4 vid6 vid7 fs isen3- pvcc3 vid5 isen3+ lgate3 boot3 ugate3 vid3 vid2 vid1 vid0 vrsel drsel ovpsel ss vcc en isen1+ isen1- phase1 ugate1 boot1 lgate1 pvcc1_2 lgate2 boot2 comp fb iout vdiff rgnd vsen isen2+ isen2- isen4+ isen4- en_ph4 pwm4 ref ofs phase3 pgood ugate2 phase2 1 48 2 3 4 5 6 7 8 9 10 36 35 34 33 32 31 30 29 28 27 47 46 45 44 43 42 41 40 39 13 14 15 16 17 18 19 20 21 22 49 gnd 23 24 11 12 38 37 26 25 through shoot- protection boot ugate phase lgate logic control gate pvcc 10k pwm soft-start and fault logic drsel 20k isl6312a isl6312a
3 fn9290.4 april 29, 2010 block diagram driver vrsel dynamic vid d/a vid7 vid6 vid5 vid4 vid3 vid2 e/a ref fb ofs comp rgnd vsen vdiff isen3- isen3+ isen4- 1 n pwm1 boot1 ugate1 phase1 lgate1 pvcc1_ 2 boot2 ugate2 phase2 lgate2 boot3 ugate3 phase3 lgate3 pvcc3 clock and generator modulator soft-start and fault logic channel detect vcc reset power-on 0.85v en fs pgood gnd 0.2v x1 isen4+ vid1 vid0 en_ph4 ph4 por/ pwm4 ch1 current sense channel current balance overvoltage detection logic undervoltage detection logic pwm2 pwm3 pwm4 mode / dac select isen1- isen1+ isen2- isen2+ ch2 current sense ch3 current sense ch4 current sense i_avg mosfet driver mosfet driver mosfet load apply transient enhancement pwm4 signal logic ocp v ocp i_avg ovpsel iout ss drsel detect waveform x1 offset oc i_trip open sense line prevention isl6312a isl6312a
4 fn9290.4 april 29, 2010 typical application - isl6312a (4-phase) vid4 vid5 pgood vid3 vid2 vid1 vcc isl6312a vid0 fs ofs ref en_ph4 pwm4 load vrsel en +12v gnd +12v +12v vid6 vid7 ss +5v isen4- isen4+ isen3- isen3+ isen2- isen2+ isen1- isen1+ ovpsel fb comp vsen rgnd vdiff drsel +12v phase1 ugate1 boot1 lgate1 +12v phase2 ugate2 boot2 lgate2 pvcc1_2 +12v phase3 ugate3 boot3 lgate3 pvcc3 iout pwm vcc boot ugate phase pvcc lgate gnd isl6612 isl6312a isl6312a
5 fn9290.4 april 29, 2010 typical application - isl6312a with ntc thermal compensation (4-phase) vid4 vid5 pgood vid3 vid2 vid1 fb comp vcc isl6312a vid0 fs ofs ref +12v phase2 ugate2 boot2 lgate2 en_ph4 pwm4 load vsen rgnd vrsel pvcc1_2 en +12v gnd +12v +12v vid6 vid7 ss +5v isen4- isen4+ isen3- isen3+ isen2- isen2+ isen1- isen1+ ovpsel ntc place in proximity vdiff drsel +12v phase3 ugate3 boot3 lgate3 pvcc3 +12v phase1 ugate1 boot1 lgate1 iout close pwm vcc ugate phase pvcc lgate gnd isl6612 boot isl6312a isl6312a
6 fn9290.4 april 29, 2010 absolute m aximum ratings supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v supply voltage, pvcc . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +15v boot voltage, v boot . . . . . . . . . . . . . . gnd - 0.3v to gnd + 36v boot to phase voltage, v boot-phase . . . . . . -0.3v to 15v (dc) -0.3v to 16v (<10ns, 10j) phase voltage, v phase . . . . . . . gnd - 0.3v to 15v (pvcc = 12) gnd - 8v (<400ns, 20j) to 24v (<200ns, v boot - phase = 12v) ugate voltage, v ugate . . . . . . . . v phase - 0.3v to v boot + 0.3v v phase - 3.5v (<100ns pulse width, 2j) to v boot + 0.3v lgate voltage, v lgate . . . . . . . . . . . gnd - 0.3v to pvcc + 0.3v gnd - 5v (<100ns pulse width, 2j) to pvcc + 0.3v input, output, or i/o voltage . . . . . . . . . gnd - 0.3v to vcc + 0.3v esd classification . . . . . . . . . . . . . . . . . . . . . . . class i jedec std thermal information thermal resistance ja (c/w) jc (c/w) qfn package (notes 1, 2) . . . . . . . . . . +32 +3.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions vcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5v 5% pvcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . +5v to 12v 5% ambient temperature (ISL6312ACRZ) . . . . . . . . . . . . 0c to +70c ambient temperature (isl6312airz) . . . . . . . . . . . .-40c to +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions, unless otherwise specified. parameter test conditions min (note 4) typ max (note 4) units bias supplies input bias supply current i vcc ; en = high 15 20 25 ma gate drive bias current - pvcc1_2 pin i pvcc1_2 ; en = high 2 4.3 6 ma gate drive bias current - pvcc3 pin i pvcc3 ; en = high 1 2.1 3 ma vcc por (power-on reset) threshold vcc rising 4.25 4.38 4.50 v vcc falling 3.75 3.88 4.00 v pvcc por (power-on reset) threshold pvcc rising 4.25 4.38 4.50 v pvcc falling 3.60 3.88 4.00 v pwm modulator oscillator frequency accuracy, f sw r t = 100k (0.1%) 225 250 275 khz adjustment range of switching frequency (note 3) 0.08 - 1.0 mhz oscillator ramp amplitude, v pp (note 3) - 1.50 - v control thresholds en rising threshold -0.85-v en hysteresis -110-mv en_ph4 rising threshold 1.160 1.210 1.250 v en_ph4 falling threshold 1.00 1.06 1.10 v comp shutdown threshold comp falling 0.1 0.2 0.3 v reference and dac system accuracy (1.000v to 1.600v) -0.5 - 0.5 % system accuracy (0.600v to 1.000v) -1.0 - 1.0 % system accuracy (0.375v - 0.600v) -2.0 - 2.0 % dac input low voltage (vr10, vr11) --0.4v dac input high voltage (vr10, vr11) 0.8 - - v isl6312a isl6312a
7 fn9290.4 april 29, 2010 dac input low voltage (amd) --0.6v dac input high voltage (amd) 1.0 - - v pin-adjustable offset ofs sink current accuracy (negative offset) r ofs = 10k from ofs to gnd 37.0 40.0 43.0 a ofs source current accuracy (positive offset) r ofs = 30k from ofs to vcc 50.5 53.5 56.5 a error amplifier dc gain r l = 10k to ground, (note 3) - 96 - db gain-bandwidth product c l = 100pf, r l = 10k to ground, (note 3) - 20 - mhz slew rate c l = 100pf, load = 400a, (note 3) - 8 - v/ s maximum output voltage load = 1ma 3.90 4.20 - v minimum output voltage load = -1ma - 1.30 1.5 v soft-start ramp soft-start ramp rate vr10/vr11, r s = 100k -1.563-mv/s amd - 2.063 - mv/s adjustment range of soft-start ramp rate (note 3) 0.625 - 6.25 mv/s pwm output pwm output voltage low threshold iload = 500 a--0.5v pwm output voltage high threshold iload = 500 a4.5--v current sensing current sense resistance, r isen t = +25c 297 300 303 sensed current tolerance isen1+ = isen2+ = isen3+ = isen4+ = 80a 76 80 84 a overcurrent protection overcurrent trip level - average channel normal operation 110 125 140 a dynamic vid change 143 163 183 a overcurrent trip level - individual channel normal operation 150 177 204 a dynamic vid change (note 3) 209.4 238 266.6 a protection undervoltage threshold vsen falling 55 60 65 %vid undervoltage hysteresis vsen rising - 10 - %vid overvoltage threshold during soft-start vr10/vr11 1.24 1.28 1.32 v amd 2.13 2.20 2.27 v overvoltage threshold (default) vr10/vr11, ovpsel tied to ground, vsen rising vdac + 150mv vdac + 175mv vdac + 200mv v amd, ovpsel tied to ground, vsen rising vdac + 225mv vdac + 250mv vdac + 275mv v overvoltage threshold (alternate) ovpsel tied to +5v, vsen rising vdac + 325mv vdac + 350mv vdac + 375mv v overvoltage hysteresis vsen falling - 100 - mv switching time (note 3) ugate rise time t rugate; v pvcc = 12v, 3nf load, 10% to 90% - 26 - ns electrical specifications recommended operating conditions, unless otherwise specified. (continued) parameter test conditions min (note 4) typ max (note 4) units isl6312a isl6312a
8 fn9290.4 april 29, 2010 timing diagram lgate rise time t rlgate; v pvcc = 12v, 3nf load, 10% to 90% - 18 - ns ugate fall time t fugate; v pvcc = 12v, 3nf load, 90% to 10% - 18 - ns lgate fall time t flgate; v pvcc = 12v, 3nf load, 90% to 10% - 12 - ns ugate turn-on non-overlap t pdhugate ; v pvcc = 12v, 3nf load, adaptive - 10 - ns lgate turn-on non-overlap t pdhlgate ; v pvcc = 12v, 3nf load, adaptive - 10 - ns gate drive resistance (note 3) upper drive source resistance v pvcc = 12v, 15ma source current 1.25 2.0 3.0 upper drive sink resistance v pvcc = 12v, 15ma sink current 0.9 1.65 3.0 lower drive source resistance v pvcc = 12v, 15ma source current 0.85 1.25 2.2 lower drive sink resistance v pvcc = 12v, 15ma sink current 0.60 0.80 1.35 over-temperature shutdown (note 3) thermal shutdown setpoint - 160 - c thermal recovery setpoint - 100 - c notes: 3. limits established by characterization and are not production tested. 4. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. te mperature limits established by characterization and are not production tested. electrical specifications recommended operating conditions, unless otherwise specified. (continued) parameter test conditions min (note 4) typ max (note 4) units ugate lgate t flgate t pdhugate t rugate t fugate t pdhlgate t rlgate isl6312a isl6312a
9 fn9290.4 april 29, 2010 functional pin description vcc vcc is the bias supply for the ics small-signal circuitry. connect this pin to a +5v supply and decouple using a quality 0.1 f ceramic capacitor. pvcc1_2 and pvcc3 these pins are the power supply pins for the corresponding channel mosfet drive, and can be connected to any voltage from +5v to +12v depending on the desired mosfet gate-drive level. decouple these pins with a quality 1.0 f ceramic capacitor. leaving pvcc3 unconnected or grounded programs the controller for 2-phase operation. gnd gnd is the bias and reference ground for the ic. en this pin is a threshold-sensitive (approximately 0.85v) enable input for the controller. held low, this pin disables controller operation. pulled high, the pin enables the controller for operation. fs a resistor, placed from fs to ground, sets the switching frequency of the controller. vid0, vid1, vid2, vid3, vi d4, vid5, vid6, and vid7 these are the inputs for the inte rnal dac that provides the reference voltage for output regulation. these pins respond to ttl logic thresholds. these pins are internally pulled high, to approximately 1.2v, by 40a internal current sources for intel modes of operation, and pulled low by 20a internal current sources for amd modes of ope ration. the internal pull-up current decreases to 0 as the vid voltage approaches the internal pull-up voltage. all vid pins are compatible with external pull-up voltages not exceeding the ic?s bias voltage (vcc). vrsel the state of this pin selects which of the available dac tables will be used to decode the vid inputs and puts the controller into the corresponding mode of operation. for vr10 mode of operation, vrsel should be less then 0.6v. the vr11 mode of operation can be selected by setting vrsel between 0.6v and 3.0v, and amd compliance is selected if this pin is between 3.0v and vcc. the vrsel pin has an internal 40a pull-up current to approximately 2v. vsen and rgnd vsen and rgnd are inputs to the precision differential remote-sense amplifier and shou ld be connected to the sense pins of the remote load. vdiff vdiff is the output of the differential remote-sense amplifier. the voltage on this pin is equal to the difference between vsen and rgnd. fb and comp these pins are the internal error amplifier inverting input and output respectively. fb, vdiff, and comp are tied together through external r-c networks to compensate the regulator. iout the iout pin is the average channel-current sense output. connecting this pin through a resistor to ground allows the controller to set the overcurrent protection trip level. this pin pin can also be used as a load current indicator to monitor what the output load current is. ref the ref input pin is the positive inpu t of the error amplifier. it is internally connected to the dac output through a 1k resistor. a capacitor is used between the ref pin and ground to smooth the voltage transition durin g dynamic vid operations. ofs the ofs pin provides a means to program a dc current for generating an offset voltage ac ross the resistor between fb and vdiff. the offset current is generated via an external resistor and precision internal voltage references. the polarity of the offset is selected by connecting the resistor to gnd or vcc. for no offset, the ofs pin should be left unconnected. isen1-, isen1+, isen2-, isen2+, isen3-, isen3+, isen4- and isen4+ these pins are used for differenti ally sensing the corresponding channel output currents. the sensed currents are used for channel balancing, protecti on, and load line regulation. connect isen1-, isen2-, isen3-, and isen4- to the node between the rc sense elements surrounding the inductor of their respective channel. tie the isen+ pins to the vcore side of their corresponding channel?s sense capacitor. ugate1, ugate2, and ugate3 connect these pins to the corresponding upper mosfet gates. these pins are used to control the upper mosfets and are monitored for shoot -through prevention purposes. boot1, boot2 and boot3 these pins provide the bias voltage for the corresponding upper mosfet drives. connect these pins to appropriately- chosen external bootstrap ca pacitors. internal bootstrap diodes connected to the pvcc pins provide the necessary bootstrap charge. phase1, phase2 and phase3 connect these pins to the sources of the corresponding upper mosfets. these pins are the return path for the upper mosfet drives. isl6312a isl6312a
10 fn9290.4 april 29, 2010 lgate1, lgate2 and lgate3 these pins are used to control the lower mosfets. connect these pins to the corresponding lower mosfets? gates. pwm4 pulse-width modulation output. connect this pin to the pwm input pin of an intersil driver ic if 4-phase operation is desired. en_ph4 this pin has two functions. firs t, a resistor divider connected to this pin will provide a por power up synch between the on-chip and external driver. the resistor divider should be designed so that when the por-trip point of the external driver is reached the voltage on this pin should be 1.21v. the second function of this pin is disabling pwm4 for 3-phase operation. this can be accomplished by connecting this pin to a +5v supply. ss a resistor, placed from ss to ground, will set the soft-start ramp slope for the intel dac modes of operation. refer to equations 18 and 19 for proper resistor calculation. for amd modes of o peration, the soft-start ramp frequency is preset, so this pin can be left unconnected. ovpsel this pin selects the ovp trip point during normal operation. leaving it unconnected or tieing it to ground selects the default setting of vdac+175mv for intel modes of operation and vdac+250mv for amd modes of operation. connecting this pin to vcc will select an ovp trip setting of vid+350mv for all modes of operation. drsel this pin selects the adaptive dead time scheme the internal drivers will use. if driving mosfets, tie this pin to ground to select the phase detect scheme or to a +5v supply through a 50k resistor to select the lgate detect scheme. pgood during normal operation pgood indicates whether the output voltage is within specified overvoltage and undervoltage limits. if the output voltage exceeds these limits or a reset event occurs (suc h as an overcurrent event), pgood is pulled low. pgood is always low prio r to the end of soft-start. operation multiphase power conversion microprocessor load current pr ofiles have changed to the point that using single-phase regu lators is no longer a viable solution. designing a regulator that is cost-effective, thermally sound, and efficient has become a challenge that only multiphase converters can accomplish. the isl6312a controller helps simplify implementation by integrating vital functions and requiring minimal external components. the ?block diagram? on page 3 provides a top level view of multiphase power conversion using the isl6312a controller. interleaving the switching of each channel in a multiphase converter is timed to be symmetrically out of phase with each of the other channels. in a 3-phase converte r, each channel switches 1/3 cycle after the previous chan nel and 1/3 cycle before the following channel. as a result, the three-phase converter has a combined ripple frequency three times greater than the ripple frequency of any one phase. in addition, the peak-to-peak amplitude of the combined inductor currents is reduced in proportion to the number of phases (equations 1 and 2). increased ripple frequency and lower ripple amplitude mean that the designer can use less per-channel inductance and lower total output capacitance for any performance specification. figure 1 illustrates the multiplic ative effect on output ripple frequency. the three channel currents (il1, il2, and il3) combine to form the ac ripple current and the dc load current. the ripple component has three times the ripple frequency of each individual channel current. each pwm pulse is terminated 1/3 of a cycle after the pwm pulse of the previous phase. the peak-to- peak current for each phase is about 7a, and the dc components of the inductor currents combine to feed the load. to understand the reduction of ripple current amplitude in the multiphase circuit, examine the equation representing an individual channel peak-to-peak inductor current. in equation 1, v in and v out are the input and output voltages respectively, l is the single-channel inductor value, and f s is the switching frequency. figure 1. pwm and inductor-current waveforms for 3-phase converter 1 s/div pwm2, 5v/div pwm1, 5v/div il2, 7a/div il1, 7a/div il1 + il2 + il3, 7a/div il3, 7a/div pwm3, 5v/div (eq. 1) i pp ? () v in v out ? () v out ? lf s v ? in ? --------------------------------------------------------- - = isl6312a isl6312a
11 fn9290.4 april 29, 2010 the output capacitors conduct the ripple component of the inductor current. in the case of multiphase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. compare equation 1 to the expression for the peak-to-peak current after the summation of n symmetrically phase-shi fted inductor currents in equation 2. peak-to-peak ripple current decreases by an amount proportional to the number of channels. output voltage ripple is a function of capacitance, capacitor equivalent series resistance (esr), and inductor ripple current. reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. another benefit of interleaving is to reduce input ripple current. input capacitance is determined in part by the maximum input ripple current. multiphase topologies can improve overall system cost and size by lo wering input ripple current and allowing the designer to reduce the cost of input capacitance. the example in figure 2 illustrates input currents from a three-phase converter combining to reduce the total input ripple current. the converter depicted in figure 2 delivers 1.5v to a 36a load from a 12v input. the rms inpu t capacitor current is 5.9a. compare this to a single-phase converter also stepping down 12v to 1.5v at 36a. the sing le-phase converter has 11.9a rms input capacitor current. the single-phase converter must use an input capacitor bank with twice the rms current capacity as the equivalent three-phase converter. active pulse positioning (app) modulated pwm operation the isl6312a uses a proprietary active pulse positioning (app) modulation scheme to control the internal pwm signals that command each channel?s driver to turn their upper and lower mosfets on and off. the time interval in which a pwm signal can occur is generated by an internal clock, whose cycle time is t he inverse of the switching frequency set by the resistor between the fs pin and ground. the advantage of intersil?s proprietary active pulse positioning (app) modulator is that the pwm signal has the ability to turn on at any point during this pwm time interval, and turn off immediately after the pwm signal has transitioned high. this is important because is allows the controller to quickly respond to output voltage drops associated with current load spikes, while avoiding the ring back affects associated wit h other modulation schemes. the pwm output state is driven by the position of the error amplifier output signal, v comp , minus the current correction signal relative to the proprie tary modulator ramp waveform as illustrated in figure 3. at the beginning of each pwm time interval, this modified v comp signal is compared to the internal modulator waveform. as long as the modified v comp voltage is lower then the modulator waveform voltage, the pwm signal is commanded low. the internal mosfet driver detects the low state of the pwm signal and turns off the upper mosfet and turns on the lower synchronous mosfet. when the modified v comp voltage crosses the modulator ramp, the pwm output transitions high, turning off the synchronous mosfet and turning on the upper mosfet. the pwm signal will remain high until the modified v comp voltage crosses the modulator ramp again. when this occurs the pwm signal will transition low again. during each pwm time interval the pwm signal can only transition high once. once pwm transitions high it can not transition high again until the beginning of the next pwm time interval. this prevents the occurrence of double pwm pulses occurring during a single period. to further improve the transient response, isl6312a also implements intersil?s proprietary adaptive phase alignment (apa) technique, which turns on all phases together under transient events with large step current. with both app and apa control, isl6312a can achieve excellent transient performance and reduce the demand on the output capacitors. channel-current balance one important benefit of mult iphase operation is the thermal advantage gained by distributing the dissipated heat over multiple devices and greater area. by doing this the designer avoids the complexity of driving parallel mosfets and the expense of using expensive he at sinks and exotic magnetic materials. in order to realize the thermal advantage, it is important that each channel in a multiphase converter be controlled to carry equal amounts of current at any load level. to achieve this, the currents through each channel must be sampled every switching cycle. t he sampled currents, i n , from each active channel are summed together and divided by the number of active channels. the resulting cycle average current, i avg , provides a measure of the total load-current (eq. 2) i cpp , v in nv out ? ? () v out ? lf s v ? in ? ------------------------------------------------------------------- - = figure 2. channel input currents and input- capacitor rms current for 3-phase converter channel 1 input current 10a/div channel 2 input current 10a/div channel 3 input current 10a/div input-capacitor current, 10a/div 1 s/div isl6312a isl6312a
12 fn9290.4 april 29, 2010 demand on the converter durin g each switching cycle. channel-current balance is achieved by comparing the sampled current of each ch annel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. intersil?s patented current- balance method is illustrate d in figure 3, with error correction for channel 1 repres ented. in the fi gure, the cycle average current, i avg , is compared with the channel 1 sample, i 1 , to create an error signal i er . the filtered error signal modifies the pulse width commanded by v comp to correct any unbalance and force i er toward zero. the same method for error signal correction is applied to each active channel. continuous current sampling in order to realize proper current-balance, the currents in each channel are sensed continuously every switching cycle. during this time the current-sense amplifier uses the isen inputs to reproduce a signal proportional to the inductor current, i l . this sensed current, i sen , is simply a scaled version of the inductor current. the isl6312a supports inductor dcr current sensing to continuously sense each channel?s current for channel-current balance. the internal circuitry, shown in figure 5 represents channel n of an n-channel converter. this circuitry is repeated for ea ch channel in the converter, but may not be active depending on how many channels are operating. inductor windings have a ch aracteristic distributed resistance or dcr (direct current resistance). for simplicity, the inductor dcr is considered as a separate lumped quantity, as shown in figure 5. the channel current i l , flowing through the inductor, passes through the dcr. equation 3 shows the s-domain equivalent voltage, v l , across the inductor. a simple r-c network across the inductor (r 1 and c) extracts the dcr voltage, as sh own in figure 5. the voltage across the sense capacitor, v c , can be shown to be proportional to the channel current i l , shown in equation 4. in some cases it may be necessa ry to use a resistor divider r-c network to sense the curr ent through the inductor. this can be accomplished by placing a second resistor, r 2 , across the sense capacitor. in these cases the voltage across the sense capacitor, v c , becomes proportional to the channel current i l , and the resistor divider ratio, k. figure 3. channel-1 pwm function and current- balance adjustment n i avg i 3 i 2 - + + - + - f(s) pwm1 i 1 v comp i er note: channel 3 and 4 are optional. filter to gate control logic i 4 modulator ramp waveform figure 4. continuous current sampling time pwm i l i sen switching period figure 5. inductor dcr current sensing configuration i n - + isen-(n) sample isl6312a internal circuit v in ugate(n) r isen dcr l inductor r 1 v out c out - + v c (s) c 1 i l - + v l (s) i sen r 2* v c (s) + - *r 2 is optional isen+(n) lgate(n) mosfet driver v l s () i l sl dcr + ? () ? = (eq. 3) v c s () sl ? dcr ------------- 1 + ?? ?? sr 1 c ?? 1 + () ------------------------------------- - dcr i l ? ? = (eq. 4) isl6312a isl6312a
13 fn9290.4 april 29, 2010 if the r-c network components are selected such that the rc time constant matches the inductor l/dcr time constant, then v c is equal to the voltage drop across the dcr multiplied by the ratio of the resistor divider, k. if a resistor divider is not being used, the value for k is 1 . the capacitor voltage v c , is then replicated across the sense resistor r isen . the current through r isen is proportional to the inductor current. equation 7 shows that the proportion between the ch annel current and the sensed current (i sen ) is driven by the value of the sense resistor, the resistor divider ratio, and the dcr of the inductor. output voltage setting the isl6312a uses a digital to analog converter (dac) to generate a reference voltage based on the logic signals at the vid pins. the dac decodes the logic signals into one of the discrete voltages shown in tables 2, 3, 4 and 5. in intel modes of operation, each vid pin is pulled up to an internal 1.2v voltage by a weak current source (40a), which decreases to 0a as the voltage at the vid pin varies from 0 to the internal 1.2v pull-up voltage. in amd modes of operation the vid pins are pulled low by a weak 20a current source. external pull-up resistors or active-high output stages can augment the pu ll-up current sources, up to a voltage of 5v. the isl6312a accommodates four different dac ranges: intel vr10 (extended), intel vr11, amd k8/k9 5-bit, and amd 6-bit. the state of the vrsel and vid7 pins decide which dac version is active. refer to table 1 for a description of how to select the desired dac version. table 1. isl6312a dac select table dac version vrsel pin vid7 pin vr10(extended) vrsel < 0.6v - vr11 0.8v < vrsel < 3.0v - amd 5-bit 3.0v < vrsel < vcc low amd 6-bit 3.0v < vrsel < vcc high v c s () sl ? dcr ------------- 1 + ?? ?? s r 1 r 2 ? () r 1 r 2 + ----------------------- - c ?? 1 + ?? ?? ?? ------------------------------------------------------- - kdcri l ?? ? = (eq. 5) k r 2 r 2 r 1 + -------------------- - = (eq. 6) i sen ki l dcr r isen ----------------- - ?? = (eq. 7) table 2. vr10 (extended) voltage identification codes vid4 vid3 vid2 vid1 vid0 vid5 vid6 vdac 0 1 0 1 0 1 1 1.60000 0 1 0 1 0 1 0 1.59375 0 1 0 1 1 0 1 1.58750 0 1 0 1 1 0 0 1.58125 0 1 0 1 1 1 1 1.57500 0 1 0 1 1 1 0 1.56875 0 1 1 0 0 0 1 1.56250 0 1 1 0 0 0 0 1.55625 0 1 1 0 0 1 1 1.55000 0 1 1 0 0 1 0 1.54375 0 1 1 0 1 0 1 1.53750 0 1 1 0 1 0 0 1.53125 0 1 1 0 1 1 1 1.52500 0 1 1 0 1 1 0 1.51875 0 1 1 1 0 0 1 1.51250 0 1 1 1 0 0 0 1.50625 0 1 1 1 0 1 1 1.50000 0 1 1 1 0 1 0 1.49375 0 1 1 1 1 0 1 1.48750 0 1 1 1 1 0 0 1.48125 0 1 1 1 1 1 1 1.47500 0 1 1 1 1 1 0 1.46875 1 0 0 0 0 0 1 1.46250 1 0 0 0 0 0 0 1.45625 1 0 0 0 0 1 1 1.45000 1 0 0 0 0 1 0 1.44375 1 0 0 0 1 0 1 1.43750 1 0 0 0 1 0 0 1.43125 1 0 0 0 1 1 1 1.42500 1 0 0 0 1 1 0 1.41875 1 0 0 1 0 0 1 1.41250 1 0 0 1 0 0 0 1.40625 1 0 0 1 0 1 1 1.40000 1 0 0 1 0 1 0 1.39375 1 0 0 1 1 0 1 1.38750 1 0 0 1 1 0 0 1.38125 1 0 0 1 1 1 1 1.37500 1 0 0 1 1 1 0 1.36875 1 0 1 0 0 0 1 1.36250 isl6312a
14 fn9290.4 april 29, 2010 1 0 1 0 0 0 0 1.35625 1 0 1 0 0 1 1 1.35000 1 0 1 0 0 1 0 1.34375 1 0 1 0 1 0 1 1.33750 1 0 1 0 1 0 0 1.33125 1 0 1 0 1 1 1 1.32500 1 0 1 0 1 1 0 1.31875 1 0 1 1 0 0 1 1.31250 1 0 1 1 0 0 0 1.30625 1 0 1 1 0 1 1 1.30000 1 0 1 1 0 1 0 1.29375 1 0 1 1 1 0 1 1.28750 1 0 1 1 1 0 0 1.28125 1 0 1 1 1 1 1 1.27500 1 0 1 1 1 1 0 1.26875 1 1 0 0 0 0 1 1.26250 1 1 0 0 0 0 0 1.25625 1 1 0 0 0 1 1 1.25000 1 1 0 0 0 1 0 1.24375 1 1 0 0 1 0 1 1.23750 1 1 0 0 1 0 0 1.23125 1 1 0 0 1 1 1 1.22500 1 1 0 0 1 1 0 1.21875 1 1 0 1 0 0 1 1.21250 1 1 0 1 0 0 0 1.20625 1 1 0 1 0 1 1 1.20000 1 1 0 1 0 1 0 1.19375 1 1 0 1 1 0 1 1.18750 1 1 0 1 1 0 0 1.18125 1 1 0 1 1 1 1 1.17500 1 1 0 1 1 1 0 1.16875 1 1 1 0 0 0 1 1.16250 1 1 1 0 0 0 0 1.15625 1 1 1 0 0 1 1 1.15000 1 1 1 0 0 1 0 1.14375 1 1 1 0 1 0 1 1.13750 1 1 1 0 1 0 0 1.13125 1 1 1 0 1 1 1 1.12500 1 1 1 0 1 1 0 1.11875 table 2. vr10 (extended) voltage identification codes (continued) vid4 vid3 vid2 vid1 vid0 vid5 vid6 vdac 1 1 1 1 0 0 1 1.11250 1 1 1 1 0 0 0 1.10625 1 1 1 1 0 1 1 1.10000 1 1 1 1 0 1 0 1.09375 1111101off 1111100off 1111111off 1111110off 0 0 0 0 0 0 1 1.08750 0 0 0 0 0 0 0 1.08125 0 0 0 0 0 1 1 1.07500 0 0 0 0 0 1 0 1.06875 0 0 0 0 1 0 1 1.06250 0 0 0 0 1 0 0 1.05625 0 0 0 0 1 1 1 1.05000 0 0 0 0 1 1 0 1.04375 0 0 0 1 0 0 1 1.03750 0 0 0 1 0 0 0 1.03125 0 0 0 1 0 1 1 1.02500 0 0 0 1 0 1 0 1.01875 0 0 0 1 1 0 1 1.01250 0 0 0 1 1 0 0 1.00625 0 0 0 1 1 1 1 1.00000 0 0 0 1 1 1 0 0.99375 0 0 1 0 0 0 1 0.98750 0 0 1 0 0 0 0 0.98125 0 0 1 0 0 1 1 0.97500 0 0 1 0 0 1 0 0.96875 0 0 1 0 1 0 1 0.96250 0 0 1 0 1 0 0 0.95625 0 0 1 0 1 1 1 0.95000 0 0 1 0 1 1 0 0.94375 0 0 1 1 0 0 1 0.93750 0 0 1 1 0 0 0 0.93125 0 0 1 1 0 1 1 0.92500 0 0 1 1 0 1 0 0.91875 0 0 1 1 1 0 1 0.91250 0 0 1 1 1 0 0 0.90625 0 0 1 1 1 1 1 0.90000 table 2. vr10 (extended) voltage identification codes (continued) vid4 vid3 vid2 vid1 vid0 vid5 vid6 vdac isl6312a
15 fn9290.4 april 29, 2010 0 0 1 1 1 1 0 0.89375 0 1 0 0 0 0 1 0.88750 0 1 0 0 0 0 0 0.88125 0 1 0 0 0 1 1 0.87500 0 1 0 0 0 1 0 0.86875 0 1 0 0 1 0 1 0.86250 0 1 0 0 1 0 0 0.85625 0 1 0 0 1 1 1 0.85000 0 1 0 0 1 1 0 0.84375 0 1 0 1 0 0 1 0.83750 0 1 0 1 0 0 0 0.83125 table 3. vr11 voltage identification codes vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac 00000000off 00000001off 000000101.60000 000000111.59375 000001001.58750 000001011.58125 000001101.57500 000001111.56875 000010001.56250 000010011.55625 000010101.55000 000010111.54375 000011001.53750 000011011.53125 000011101.52500 000011111.51875 000100001.51250 000100011.50625 000100101.50000 000100111.49375 000101001.48750 000101011.48125 000101101.47500 000101111.46875 000110001.46250 table 2. vr10 (extended) voltage identification codes (continued) vid4 vid3 vid2 vid1 vid0 vid5 vid6 vdac 000110011.4 5625 000110101.4 5000 000110111.4 4375 000111001.4 3750 000111011.4 3125 000111101.4 2500 000111111.4 1875 001000001.4 1250 001000011.4 0625 001000101.4 0000 001000111.3 9375 001001001.3 8750 001001011.3 8125 001001101.3 7500 001001111.3 6875 001010001.3 6250 001010011.3 5625 001010101.3 5000 001010111.3 4375 001011001.3 3750 001011011.3 3125 001011101.3 2500 001011111.3 1875 001100001.3 1250 001100011.3 0625 001100101.3 0000 001100111.2 9375 001101001.2 8750 001101011.2 8125 001101101.2 7500 001101111.2 6875 001110001.2 6250 001110011.2 5625 001110101.2 5000 001110111.2 4375 001111001.2 3750 001111011.2 3125 001111101.2 2500 001111111.2 1875 table 3. vr11 voltage identification codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac isl6312a
16 fn9290.4 april 29, 2010 010000001.21250 010000011.20625 010000101.20000 010000111.19375 010001001.18750 010001011.18125 010001101.17500 010001111.16875 010010001.16250 010010011.15625 010010101.15000 010010111.14375 010011001.13750 010011011.13125 010011101.12500 010011111.11875 010100001.11250 010100011.10625 010100101.10000 010100111.09375 010101001.08750 010101011.08125 010101101.07500 010101111.06875 010110001.06250 010110011.05625 010110101.05000 010110111.04375 010111001.03750 010111011.03125 010111101.02500 010111111.01875 011000001.01250 011000011.00625 011000101.00000 011000110.99375 011001000.98750 011001010.98125 011001100.97500 table 3. vr11 voltage identification codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac 011001110.9 6875 011010000.9 6250 011010010.9 5625 011010100.9 5000 011010110.9 4375 011011000.9 3750 011011010.9 3125 011011100.9 2500 011011110.9 1875 011100000.9 1250 011100010.9 0625 011100100.9 0000 011100110.8 9375 011101000.8 8750 011101010.8 8125 011101100.8 7500 011101110.8 6875 011110000.8 6250 011110010.8 5625 011110100.8 5000 011110110.8 4375 011111000.8 3750 011111010.8 3125 011111100.8 2500 011111110.8 1875 100000000.8 1250 100000010.8 0625 100000100.8 0000 100000110.7 9375 100001000.7 8750 100001010.7 8125 100001100.7 7500 100001110.7 6875 100010000.7 6250 100010010.7 5625 100010100.7 5000 100010110.7 4375 100011000.7 3750 100011010.7 3125 table 3. vr11 voltage identification codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac isl6312a
17 fn9290.4 april 29, 2010 100011100.72500 100011110.71875 100100000.71250 100100010.70625 100100100.70000 100100110.69375 100101000.68750 100101010.68125 100101100.67500 100101110.66875 100110000.66250 100110010.65625 100110100.65000 100110110.64375 100111000.63750 100111010.63125 100111100.62500 100111110.61875 101000000.61250 101000010.60625 101000100.60000 101000110.59375 101001000.58750 101001010.58125 101001100.57500 101001110.56875 101010000.56250 101010010.55625 101010100.55000 101010110.54375 101011000.53750 101011010.53125 101011100.52500 101011110.51875 101100000.51250 101100010.50625 101100100.50000 11111110off 11111111off table 3. vr11 voltage identification codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac table 4. amd 5-bit voltage identification codes vid4 vid3 vid2 vid1 vid0 vdac 11111off 111100.800 111010.825 111000.850 110110.875 110100.900 110010.925 110000.950 101110.975 101101.000 101011.025 101001.050 100111.075 100101.100 100011.125 100001.150 011111.175 011101.200 011011.225 011001.250 010111.275 010101.300 010011.325 010001.350 001111.375 001101.400 001011.425 001001.450 000111.475 000101.500 000011.525 000001.550 table 5. amd 6-bit voltage identification codes vid5 vid4 vid3 vid2 vid1 vid0 vdac 0 0 0 0 0 0 1.5500 0 0 0 0 0 1 1.5250 0 0 0 0 1 0 1.5000 0 0 0 0 1 1 1.4750 isl6312a
18 fn9290.4 april 29, 2010 voltage regulation the integrating compensation network shown in figure 6 insures that the steady-state error in the output voltage is limited only to the error in the reference voltage (output of the dac) and offset errors in the ofs current source, remote-sense and error amplifiers. intersil specifies the guaranteed tolerance of the isl6312a to include the combined tolerances of each of these elements. the output of the error amplifier, v comp , is compared to the triangle waveform to generate the pwm signals. the pwm signals control the timing of the internal mosfet drivers and regulate the converter output so that the voltage at fb is equal to the voltage at ref. this will regulate the output voltage to be equal to equation 8. the internal and external circuitry that controls voltage regulation is illustrated in figure 6. the isl6312a incorporates an internal differential remote- sense amplifier in the feedba ck path. the amplifier removes the voltage error encountered when measuring the output voltage relative to the controller ground reference point 0 0 0 1 0 0 1.4500 0 0 0 1 0 1 1.4250 0 0 0 1 1 0 1.4000 0 0 0 1 1 1 1.3750 0 0 1 0 0 0 1.3500 0 0 1 0 0 1 1.3250 0 0 1 0 1 0 1.3000 0 0 1 0 1 1 1.2750 0 0 1 1 0 0 1.2500 0 0 1 1 0 1 1.2250 0 0 1 1 1 0 1.2000 0 0 1 1 1 1 1.1750 0 1 0 0 0 0 1.1500 0 1 0 0 0 1 1.1250 0 1 0 0 1 0 1.1000 0 1 0 0 1 1 1.0750 0 1 0 1 0 0 1.0500 0 1 0 1 0 1 1.0250 0 1 0 1 1 0 1.0000 0 1 0 1 1 1 0.9750 0 1 1 0 0 0 0.9500 0 1 1 0 0 1 0.9250 0 1 1 0 1 0 0.9000 0 1 1 0 1 1 0.8750 0 1 1 1 0 0 0.8500 0 1 1 1 0 1 0.8250 0 1 1 1 1 0 0.8000 0 1 1 1 1 1 0.7750 1 0 0 0 0 0 0.7625 1 0 0 0 0 1 0.7500 1 0 0 0 1 0 0.7375 1 0 0 0 1 1 0.7250 1 0 0 1 0 0 0.7125 1 0 0 1 0 1 0.7000 1 0 0 1 1 0 0.6875 1 0 0 1 1 1 0.6750 1 0 1 0 0 0 0.6625 1 0 1 0 0 1 0.6500 1 0 1 0 1 0 0.6375 table 5. amd 6-bit voltage identification codes (continued) vid5 vid4 vid3 vid2 vid1 vid0 vdac 1 0 1 0 1 1 0.6250 1 0 1 1 0 0 0.6125 1 0 1 1 0 1 0.6000 1 0 1 1 1 0 0.5875 1 0 1 1 1 1 0.5750 1 1 0 0 0 0 0.5625 1 1 0 0 0 1 0.5500 1 1 0 0 1 0 0.5375 1 1 0 0 1 1 0.5250 1 1 0 1 0 0 0.5125 1 1 0 1 0 1 0.5000 1 1 0 1 1 0 0.4875 1 1 0 1 1 1 0.4750 1 1 1 0 0 0 0.4625 1 1 1 0 0 1 0.4500 1 1 1 0 1 0 0.4375 1 1 1 0 1 1 0.4250 1 1 1 1 0 0 0.4125 1 1 1 1 0 1 0.4000 1 1 1 1 1 0 0.3875 1 1 1 1 1 1 0.3750 table 5. amd 6-bit voltage identification codes (continued) vid5 vid4 vid3 vid2 vid1 vid0 vdac v out v ref v ofs ? v droop ? = (eq. 8) isl6312a
19 fn9290.4 april 29, 2010 resulting in a more accurate means of sensing output voltage. connect the microprocessor sense pins to the non-inverting input, vsen, and in verting input, rgnd, of the remote-sense amplifier. the remote-sense output, v diff , is connected to the inverting input of the error amplifier through an external resistor. load-line (droop) regulation some microprocessor manufact urers require a precisely controlled output resistance. this dependence of output voltage on load current is often termed ?droop? or ?load line? regulation. by adding a well controlled output impedance, the output voltage can effectively be level shifted in a direction which works to achieve the load-line regulation required by these manufacturers. in other cases, the designer may determine that a more cost-effective solution can be achieved by adding droop. droop can help to reduce the output-voltage spike that results from fast load-current demand changes. the magnitude of the spike is dictated by the esr and esl of the output capacitors selected. by positioning the no-load voltage level near the upper s pecification limit, a larger negative spike can be sustained without crossing the lower limit. by adding a well cont rolled output impedance, the output voltage under load can effectively be level shifted down so that a larger positive spike can be sustained without crossing the upper specification limit. as shown in figure 6, a current proportional to the average current of all active channels, i avg , flows from fb through a load-line regulation resistor r fb . the resulting voltage drop across r fb is proportional to the output current, effectively creating an output voltage dro op with a steady-state value defined as: the regulated output voltage is reduced by the droop voltage v droop . the output voltage as a function of load current is derived by combining equations 7, 8, and 9. in equation 10, v ref is the reference voltage, v ofs is the programmed offset voltage, i out is the total output current of the converter, r isen is the internal sense resistor connected to the isen+ pin, r fb is the feedback resistor, n is the active channel number, and dcr is the inductor dcr value. therefore the equivalent loadl ine impedance, i.e. droop impedance, is equal to equation 11: output-voltage offset programming the isl6312a allows the designer to accurately adjust the offset voltage by connecting a resistor, r ofs , from the ofs pin to vcc or gnd. when r ofs is connected between ofs and vcc, the voltage across it is regulated to 1.6v. this causes a proportional current (i ofs ) to flow into the fb pin. if r ofs is connected to ground, the voltage across it is regulated to 0.4v, and i ofs flows out of the fb pin. the offset current flowing through the resistor between vdiff and fb will generate the desired offset voltage which is equal to the product (i ofs x r fb ). these functions are shown in figures 7 and 8. once the desired output offset voltage has been determined, use the following formulas to set r ofs : for negative offset (connect r ofs to gnd): for positive offset (connect r ofs to vcc): figure 6. output voltage and load-line regulation with offset adjustment i avg external circuit isl6312a internal circuit comp r c r fb fb vdiff vsen rgnd - + (v droop + v ofs ) error - + v out + differential remote-sense amplifier v comp c c ref c ref - + v out - vid dac 1k amplifier i ofs (eq. 9) v droop i avg r fb ? = (eq. 10) v out v ref v ofs ? i out n ------------- dcr r isen ----------------- - r fb ?? ?? ?? ?? ? = r ll r fb n ------------ dcr r isen ----------------- - ? = (eq. 11) (eq. 12) r ofs 0.4 r fb ? v offset -------------------------- = (eq. 13) r ofs 1.6 r fb ? v offset -------------------------- = isl6312a
20 fn9290.4 april 29, 2010 dynamic vid modern microprocessors need to make changes to their core voltage as part of normal operation. they direct the isl6312a to do this by making changes to the vid inputs. the isl6312a is required to monitor the dac inputs and respond to on-the-fly vid changes in a co ntrolled manner, supervising a safe output voltage transition without discontinuity or disruption. the dac mode the isl6312a is operating in determines how the controller responds to a dynamic vid change. intel dynamic vid transitions when in intel vr10 or vr11 mode the isl6312a checks the vid inputs on the positive edge of an internal 3mhz clock. if a new code is established and it remains stable for 3 consecutive readings (1s to 1.33s), the isl6312a recognizes the new code and changes the internal dac reference directly to the new level. the intel processor controls the vid transitions and is responsible for incrementing or decrementing one vid step at a time. in vr10 and vr11 settings, the isl6312a will immediately change the internal dac reference to the new requested value as soon as the request is validated, which means the fastest recommended rate at which a bit change can occur is once every 2s. in cases where the refe rence step is too large, the sudden change can trigger overcurrent or overvoltage events. in order to ensure the smooth transition of output voltage during a vr10 or vr11 vid change, a vid step change smoothing network is required. this network is composed of an internal 1k resistor between the dac and the ref pin, and the external capacitor c ref , between the ref pin and ground. the selection of c ref is based on the time duration for 1 bit vid change and the allowable delay time. assuming the microprocessor co ntrols the vid change at 1 bit every t vid , the relationship between c ref and t vid is given by equation 14. as an example, for a vid step change rate of 5 s per bit, the value of c ref is 5600pf based on equation 14. amd dynamic vid transitions when running in amd 5-bit or 6- bit modes of operation, the isl6312a responds differently to a dynamic vid change then when in intel vr10 or vr11 mode. in the amd modes the isl6312a still checks the vid inputs on the positive edge of an internal 3mhz clock. in these modes the vid code can be changed by more than a 1-bit step at a time. if a new code is established and it remains stable for 3 consecutive readings (1 s to 1.33 s), the isl6312a recognizes the change and begins slewing the dac in 6.25mv steps at a stepping frequency of 330khz until the vid and dac are equal. thus, the total time required for a vid change, t dvid , is dependent only on the size of the vid change ( v vid ). the time required for a isl6312a-based converter in amd 5-bit dac configuration to make a 1. 1v to 1.5v reference voltage change is about 194s, as calculated using equation 15. in order to ensure the smooth transition of output voltage during an amd vid change, a vid step change smoothing network is required. this network is composed of an internal 1k resistor between the dac and the ref pin, and the external capacitor c ref , between the ref pin and ground. for amd vid transitions c ref should be a 1000pf capacitor. e/a fb ofs vcc + 1.6v vcc r ofs r fb vdiff isl6312a figure 7. positive offset output voltage programming ref v ofs + - i ofs i ofs 1:1 current mirror - figure 8. negative offset output voltage programming e/a fb ofs gnd + 0.4v r ofs r fb vdiff isl6312a ref v ofs + - i ofs i ofs 1:1 current mirror vcc - gnd (eq. 14) c ref 0.001 s () t vid ? = (eq. 15) t dvid 1 330 10 3 ------------------------- - v vid 0.00625 --------------------- ?? ?? ? = isl6312a
21 fn9290.4 april 29, 2010 user selectable adaptive deadtime control techniques the isl6312a integrated driver s incorporate two different adaptive deadtime control techniques, which the user can choose between. both of thes e control techniques help to minimize deadtime, resulting in high efficiency from the reduced freewheeling time of the lower mosfet body-diode conduction, and both help to prevent the upper and lower mosfets from conducting simultaneously. this is accomplished by ensuring either rising gate turns on its mosfet with minimum and sufficient delay after the other has turned off. the difference between the two adaptive deadtime control techniques is the method in which they detect that the lower mosfet has transitioned off in order to turn on the upper mosfet. the state of the drsel pin chooses which of the two control techniques is active. by tying the drsel pin directly to ground, the phase detect scheme is chosen, which monitors the voltage on the phase pin to determine if the lower mosfet has transitioned off or not. tying the drsel pin to vcc though a 50k resistor selects the lgate detect scheme, which monitors the voltage on the lgate pin to determine if the lower mosfet has turned off or not. for both schemes, the method for determining whether the upper mosfet has transitioned off in order to signal to turn on the lower mosfet is the same. phase detect if the drsel pin is tied direct ly to ground, the phase detect adaptive deadtime control technique is selected. for the phase detect scheme, during turn -off of the lower mosfet, the phase voltage is monitored until it reaches a -0.3v/+0.8v (forward/reverse induct or current). at this time the ugate is released to rise. an auto-zero comparator is used to correct the r ds(on) drop in the phase voltage pr eventing false detection of the -0.3v phase level during r ds(on) conduction period. in the case of zero current, the ugate is released after 35ns delay of the lgate dropping below 0.5v. when lgate first begins to transition low, this quick tran sition can dist urb the phase node and cause a false trip, so there is 20ns of blanking time once lgate falls until phase is monitored. once the phase is high , the advanced adaptive shoot-through circuitry mo nitors the phase and ugate voltages during a pwm falling edge and the subsequent ugate turn-off. if either the ugate falls to less than 1.75v above the phase or the phase fall s to less than +0.8v, the lgate is released to turn-on. lgate detect if the drsel pin is tied to vcc through a 50k resistor, the lgate detect adaptive deadtime control technique is selected. for the lgate detect scheme, du ring turn-off of the lower mosfet, the lgate voltage is monitored until it reaches 1.75v. at this time the ugate is released to rise. once the phase is high, the advanced adaptive shoot-through circuitry monitors the phase and ugate voltages during a pwm falling edge and the subsequent ugate turn-off. if either the ugate falls to less than 1.75v above the phase or the phase fa lls to less than +0.8v, the lgate is released to turn on. internal bootstrap device all three integrated drivers feature an internal bootstrap schottky diode. simply adding an external capacitor across the boot and phase pins completes the bootstrap circuit. the bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to the large negative swing at the phase node. this reduces voltage stress on the boot to phase pins. the bootstrap capacitor must have a maximum voltage rating above pvcc + 4v and its capacitance value can be chosen from equation 16: where q g1 is the amount of gate charge per upper mosfet at v gs1 gate-source voltage and n q1 is the number of control mosfets. the v boot_cap term is defined as the allowabl e droop in the rail of the upper gate drive. gate drive voltage versatility the isl6312a provides the user flexibility in choosing the gate drive voltage for efficiency optimization. the controller ties the upper and lower drive rails together. simply applying a voltage from 5v up to 12v on pvcc sets both gate drive rail voltages simultaneously. 50nc 20nc figure 9. bootstrap capacitance vs boot ripple voltage v boot_cap (v) c boot_cap ( f) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 q gate = 100nc c boot_cap q gate v boot_cap -------------------------------------- q gate q g1 pvcc ? v gs1 ---------------------------------- n q1 ? = (eq. 16) isl6312a
22 fn9290.4 april 29, 2010 initialization prior to initialization, proper conditions must exist on the en, vcc, pvcc and the vid pins. when the conditions are met, the controller begins soft-start. once the output voltage is within the proper window of operation, the controller asserts pgood. enable and disable while in shutdown mode, the pwm outputs are held in a high-impedance state to assure the drivers remain off. the following input conditions must be met, for both intel and amd modes of operation, before the isl6312a is released from shutdown mode to begin the soft-start start-up sequence: 1. the bias voltage applied at vcc must reach the internal power-on reset (por) rising threshold. once this threshold is reached, proper operation of all aspects of the isl6312a is guaranteed. hysteresis between the rising and falling thresholds assure that once enabled, the isl6312a will not inadvertently turn off unless the bias voltage drops substantially (see ?electrical specifications? on page 6). 2. the voltage on en must be above 0.85v. the en input allows for power sequencing between the controller bias voltage and another voltage rail. the enable comparator holds the isl6312a in shutdown until the voltage at en rises above 0.85v. the enable comparator has 110mv of hysteresis to prevent bounce. 3. the voltage on the en_ph4 pin must be above 1.21v. the en_ph4 input allows for power sequencing between the controller and the external driver. 4. the driver bias voltage applied at the pvcc pins must reach the internal power-on reset (por) rising threshold. in order for the isl6312a to begin operation, pvcc1 is the only pin that is required to have a voltage applied that exceeds por. however, for 2 or 3-phase operation pvcc2 and pvcc3 must also exceed the por threshold. hysteresis between the rising and falling thresholds assure that once enabled, the isl6312a will not inadvertently turn off unless the pvcc bias voltage drops substantially (see ?electrical specifications? on page 6). for intel vr10, vr11 and amd 6-bit modes of operation these are the only conditions that must be met for the controller to immediately begin the soft-start sequence. if running in amd 5-bit mode of operation there is one more condition that must be met: 5. the vid code must not be 11111 in amd 5-bit mode. this code signals the controller that no load is present. the controller will not allow soft-sta rt to begin if this vid code is present on the vid pins. once all of these conditions are met the controller will begin the soft-start sequence and will ramp the output voltage up to the user designated level. intel soft-start the soft-start function allows the converter to bring up the output voltage in a controlled fashion, resulting in a linear ramp-up. the soft-start sequ ence for the intel modes of operation is slightly differ ent then the amd soft-start sequence. for the intel vr10 and vr11 modes of operation, the soft-start sequence if composed of four periods, as shown in figure 11. once the isl6312a is released from shutdown and soft-start begins (as described in ?enable and disable? on page 22), the controller will have fixed delay period td1. after this delay period, the vr will begin first soft-start ramp until the output voltage reaches 1.1v vboot voltage. then, the controller will regulate the vr voltage at 1.1v for another fixed period td3. at the end of td3 period, isl6312a will read the vid signals. if the vid code is valid, isl6312a will initiate the second soft-start ramp until the output voltage reaches the vid voltage plus/minus any offset or droop voltage. the soft-start time is the sum of the 4 periods as shown in equation 17. figure 10. power sequencing using threshold- sensitive enable (en) function external circuit isl6312a internal circuit - + 0.85v en +12v por circuit 10.7k 1.40k enable comparator soft-start and fault logic vcc pvcc1 en_ph4 - + 1.21v t ss td1td2td3td4 +++ = (eq. 17) isl6312a
23 fn9290.4 april 29, 2010 td1 is a fixed delay with the typical value as 1.40ms. td3 is determined by the fixed 85s plus the time to obtain valid vid voltage. if the vid is valid before the output reaches the 1.1v, the minimum time to validate the vid input is 500ns. therefore the minimum td3 is about 86s. during td2 and td4, isl6312a digitally controls the dac voltage change at 6.25mv per step. the time for each step is determined by the frequency of the soft-start oscillator which is defined by the resistor r ss from ss pin to gnd. the second soft-start ramp time td2 and td4 can be calculated based on equations 18 and 19: for example, when vid is set to 1.5v and the r ss is set at 100k , the first soft-start ramp time td2 will be 704s and the second soft-start ramp time td4 will be 256s. note: if the ss pin is grounded, the soft-start ramp in td2 and td4 will be defaulted to a 6.25mv step frequency of 330khz. after the dac voltage reaches the final vid setting, pgood will be set to high with the fixed delay td5. the typical value for td5 is 440s. amd soft-start for the amd 5-bit and 6-bi t modes of operation, the soft-start sequence is composed of three periods, as shown in figure 12. at the beginning of soft-start, the vid code is immediately obtained from the vid pins, followed by a fixed delay period tda. after this delay period the isl6312a will begin ramping the output voltage to the desired dac level at a fixed rate of 6.25mv per step, with a stepping frequency of 330khz. the amount of time required to ramp the output voltage to the final dac voltage is referred to as tdb, and can be calculated as shown in equation 20. after the dac voltage reaches the final vid setting, pgood will be set to high with the fixed delay tdc. the typical value for tdc can range between 1.5ms and 3.0ms. pre-biased soft-start the isl6312a also has the ability to start up into a pre-charged output, without causing any unnecessary disturbance. the fb pin is moni tored during soft-start, and should it be higher than the equivalent internal ramping reference voltage, the output drives hold both mosfets off. once the internal ramping reference exceeds the fb pin potential, the output drives are enabled, allowing the output to ramp from the pre-charged level to the final level dictated by the dac setting. should the output be pre-charged to a level exceeding the dac setting, t he output drives are enabled at the end of the soft-start period, leading to an abrupt correction in the output voltage do wn to the dac-set level. figure 11. soft-start waveforms vout, 500mv/div en_vtt 500s/div td1 td2 td3 td4 td5 pgood (eq. 18) td2 1.1 r ? ss 6.25 25 ? ------------------------ s () = (eq. 19) td4 v vid 1.1 ? () r ss ? 6.25 25 ? --------------------------------------------------- - s () = (eq. 20) tdb 1 330 10 3 ------------------------- - v vid 0.00625 --------------------- ?? ?? ? = figure 12. soft-start waveforms vout, 500mv/div en_vtt 500s/div tda tdb tdc pgood figure 13. soft-start waveforms for isl6312a- based multiphase converter en (5v/div) v out (0.5v/div) gnd> t1 gnd> t2 t3 output precharged below dac level output precharged above dac level isl6312a
24 fn9290.4 april 29, 2010 fault monitoring and protection the isl6312a actively monitors output voltage and current to detect fault conditions. fault monitors trigger protective measures to prevent damage to a microprocessor load. one common power good indicator is provided for linking to external system monitors. th e schematic in figure 14 outlines the interaction between the fault monitors and the power good signal. power good signal the power good pin (pgood) is an open-drain logic output that signals whether or not the isl6312a is regulating the output voltage within the proper levels, and whether any fault conditions exist. this pin should be tied to a +5v source through a resistor. during shutdown and soft-start pgood pulls low and releases high after a successful soft-start and the output voltage is operating between the undervoltage and overvoltage limits. pgood transitions low when an undervoltage, overvoltage, or overcurrent condition is detected or when the controller is disabled by a reset from en, en_ph4, por, or one of th e no-cpu vid codes. in the event of an overvoltage or overcurrent condition, the controller latches off and pgood will not return high until after a successful soft-start. in the case of an undervoltage event, pgood will return high when the output voltage returns to within the undervoltage. overvoltage protection the isl6312a constantly monitors the sensed output voltage on the vdiff pin to detect if an overvoltage event occurs. when the output voltage rises above the ovp trip level actions are taken by the isl6312a to protect the microprocessor load. the overvoltage protection trip level changes depending on what mode of operation the controller is in and what state the ovpsel and vrsel pins are in. tables 6 and 7 list what the ovp trip levels are under all conditions. at the inception of an overvo ltage event, lgate1, lgate2 and lgate3 are commanded high, pwm4 is commanded low, and the pgood signal is driven low. this turns on the all of the lower mosfets and pulls the output voltage below a level that might cause damage to the load. the lgate outputs remain high and pwm4 remains low until vdiff falls 100mv below the ovp threshold that tripped the overvoltage protection circuitry. the isl63 12a will continue to protect the load in this fashion as long as the overvoltage condition recurs. once an overvoltage condition ends the isl6312a latches off, and must be reset by toggling en, or through por, before a soft-start can be reinitiated. one exception that overrides the overvoltage protection circuitry is a dynamic vid transi tion in amd modes of operation. if a new vid code is detected during normal operation, the ovp protection circuitry is disabled from the beginning of the dynamic vid transition, until 50s after the internal dac reaches the final vid setting. this is the only time during operation of the isl6 312a that the ovp circuitry is not active. pre-por overvoltage protection prior to pvcc and vcc exceeding their por levels, the isl6312a is designed to pr otect the load from any overvoltage events that may occur. this is accomplished by means of an internal 10k resistor tied from phase to lgate, which turns on the lower mosfet to control the output voltage until the overvolt age event ceases or the input figure 14. power good and protection circuitry - + vdac vsen - + 0.60 x dac ov uv pgood soft-start, fault and control logic v ovp isl6312a internal circuitry - + rgnd x1 +175mv, +250mv, +350mv ovpsel - + v ocp ocp - + ocl i 1 repeat for each channel 170 a vrsel vdiff iout - + 125 a i avg ocp table 6. intel vr10 and vr11 ovp thresholds mode of operation ovpsel pin open or tied to gnd ovpsel pin tied to vcc soft-start (td1 and td2) 1.280v and vdac + 175mv (higher of the two) 1.280v and vdac + 350mv (higher of the two) soft-start (td3 and td4) vdac + 175mv vdac + 350mv normal operation vdac + 175mv vdac + 350mv table 7. amd ovp thresholds mode of operation ovpsel pin open or tied to gnd ovpsel pin tied to vcc soft-start 2.200v and vdac + 250mv (higher of the two) 2.200v and vdac + 350mv (higher of the two) normal operation vdac + 250mv vdac + 350mv isl6312a
25 fn9290.4 april 29, 2010 power supply cuts off. for complete protection, the low side mosfet should have a gate threshold well below the maximum voltage rating of the load/microprocessor. in the event that during norma l operation the pvcc or vcc voltage falls back below the por threshold, the pre-por overvoltage protection circuitry reactivates to protect from any more pre-por overvoltage events. undervoltage detection the undervoltage threshold is set at 60% of the vid code. when the output voltage (vsen-rgnd) is below the undervoltage threshold, pgood gets pulled low. no other action is taken by the controller. pgood will return high if the output voltage rises ab ove 70% of the vid code. open sense line prevention in the case that either of the remote sense lines, vsen or gnd, become open, the isl6312a is designed to prevent the controller from regulating. this is accomplished by means of a small 5a pull-up current on vsen, and a pull-down current on rgnd. if the sense lines are opened at any time, the voltage difference between vsen and rgnd will increase until an overvolt age event occurs, at which point overvoltage protection activates and the controller stops regulating. the isl6312a will be latched off and cannot be restarted until the c ontroller is reset. overcurrent protection the isl6312a takes advantage of the proportionality between the load current and the average current, i avg , to detect an overcurrent condition. two different methods of detecting overcurrent events are available on the isl6312a. the first method continually compares the average sense current with a constant 125a ocp reference current as shown in figure 14. once the average sense current exceeds the ocp reference current, a comparator triggers the converter to begin overcu rrent protection procedures. this first method for detectin g overcurrent events limits the minimum overcurrent trip threshold because of the fact the isl6312a uses set internal r isen current sense resistors. for this first method the minimu m overcurrent trip threshold is dictated by the dcr of the inductors and the number of active channels. to calculate the minimum overcurrent trip level, i ocp,min , use equation 21, where n is the number of active channels, dcr is the individual inductor?s dcr, and r isen is the 300 internal current sense resistor. if the desired overcurrent tr ip level is greater then the minimum overcurrent trip level, i ocp,min , then the resistor divider r-c circuit around the inductor shown in figure 5 should be used to set the desired trip level. if an overcurrent trip level lower then i ocp,min is desired, then a second method for setting the ocp trip level is available. the second method for detecting overcurrent events continuously compares the vo ltage on the iout pin, v iout , to the overcurrent protection voltage, v ocp , as shown in figure 14. the average channel sense current flows out the iout pin and through r iout , creating the iout pin voltage which is proportional to the output current. when the iout pin voltage exceeds the v ocp voltage of 2.0v, the overcurrent protection circuitry activates. since the iout pin voltage is proportional to the output current, the overcurrent trip level, i ocp , can be set by selecting the proper value for r iout , as shown in equation 23. once the output current exceeds the overcurrent trip level, v iout will exceed v ocp and a comparator will trigger the converter to begin overcurrent protection procedures. at the beginning of an overcurrent shutdown, the controller turns off both upper and lower mosfets. the system remains in this state for fixed per iod of 12ms. if the controller is still enabled at the end of this wait period, it will attempt a soft-start. if the fault rema ins, the trip-retry cycles will continue indefinitely until either the controller is disabled or the fault is cleared. note that the energy delivered during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard. i ocp min , 125 10 6 ? r isen n ?? ? dcr ---------------------------------------------------------- = (eq. 21) (eq. 22) i ocp i ocp min , > i ocp 125 10 6 ? r isen n ?? ? dcr ---------------------------------------------------------- ?? ?? ?? r 1 r 2 + r 2 -------------------- - ?? ?? ?? ? = i ocp v ocp r isen n ?? dcr r iout ? ---------------------------------------------- = (eq. 23) i ocp i ocp min , < 0a 0v 3ms/div output current, 50a/div figure 15. overcurrent behavior in hiccup mode output voltage, 500mv/div isl6312a
26 fn9290.4 april 29, 2010 individual channel overcurrent limiting the isl6312a has the ability to limit the current in each individual channel without shutting down the entire regulator. this is accomplished by continuously comparing the sensed currents of each channel with a constant 170a ocl reference current as shown in figure 14. if a channel?s individual sensed current exceeds this ocl limi t, the ugate signal of that channel is immediately forced low, and the lgate signal is forced high. this turns off the upper mosfet(s), turns on the lower mosfet(s), and stops the rise of current in that channel, forcing the current in the chann el to decrease. that channel?s ugate signal will not be able to return high until the sensed channel current falls back below the 170a reference. general design guide this design guide is intended to provide a high-level explanation of the steps necessary to create a multiphase power converter. it is assumed that the reader is familiar with many of the basic skills and techniques referenced below. in addition to this guide, intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications. power stages the first step in designing a multiphase converter is to determine the number of phases . this determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. principally, the designer will be concerned with whether components can be mounted on both sides of th e circuit board, whether through-hole components are perm itted, the total board space available for power-supply circuitry, and the maximum amount of load current. generally speaking, the most economical solutions are those in which each phase handles between 25a and 30a. all surface-mount designs will tend toward the lower end of this current range. if through-hole mosfets and inductors can be used, higher per-phase currents are possible. in cases where board space is the limiting constraint, current can be pushed as high as 40a per phase, but these designs require heat sinks and forced air to cool the mosfets, inductors and heat-dissipating surfaces. mosfets the choice of mosfets depends on the current each mosfet will be required to con duct, the switching frequency, the capability of the mosfets to dissipate heat, and the availability and nature of heat sinking and air flow. lower mosfet power calculation the calculation for power loss in the lower mosfet is simple, since virtually all of the loss in the lower mosfet is due to current conducted through the channel resistance (r ds(on) ). in equation 24, i m is the maximum continuous output current, i pp is the peak-to-peak inductor curr ent (see equation 1), and d is the duty cycle (v out /v in ). an additional term can be added to the lower-mosfet loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-mosfet body diode. this term is depe ndent on the diode forward voltage at i m , v d(on) , the switching frequency, f s , and the length of dead times, t d1 and t d2 , at the beginning and the end of the lower-mo sfet conduction interval respectively. the total maximum power dissipated in each lower mosfet is approximated by the summation of p low,1 and p low,2 . upper mosfet power calculation in addition to r ds(on) losses, a large portion of the upper-mosfet losses are due to currents conducted across the input voltage (v in ) during switching. since a substantially higher portion of the upper-mosfet losses are dependent on switching frequency, the power calculation is more complex. upper mosfet losses can be divided into separate components involving the upper-mosfet switching times, the lower-mosfet body-diode reverse-recovery charge, q rr , and the upper mosfet r ds(on) conduction loss. when the upper mosfet turns of f, the lower mosfet does not conduct any portion of th e inductor current until the voltage at the phase node falls below ground. once the lower mosfet begins conducting, the current in the upper mosfet falls to zero as the current in the lower mosfet ramps up to assume the full inductor current. in equation 26, the required time for this commutation is t 1 and the approximated associated power loss is p up,1 . at turn on, the upper mosfet begins to conduct and this transition occurs over a time t 2 . in equation 27, the approximate power loss is p up,2 . a third component involves the lower mosfet reverse-recovery charge, q rr . since the inductor current has fully commutated to the upper mosfet before the lower- mosfet body diode can recover all of q rr , it is conducted through the upper mosfet across vin. the power dissipated as a result is p up,3 . finally, the resistive part of the upper mosfet is given in equation 29 as p up,4 :. (eq. 24) p low 1 , r ds on () i m n ----- - ?? ?? ?? 2 1d ? () ? i lpp , 2 1d ? () ? 12 ------------------------------------ - + ? = (eq. 25) p low 2 , v don () f s i m n ------ i pp 2 --------- - + ?? ?? ?? t d1 ? i m n ------ i pp 2 --------- - ? ?? ?? ?? ?? t d2 ? + ?? = (eq. 26) p up 1 , v in i m n ----- - i pp 2 -------- - + ?? ?? t 1 2 ---- ?? ?? ?? f s ??? p up 2 , v in i m n ----- - i pp 2 -------- - ? ?? ?? ?? t 2 2 ---- ?? ?? ?? f s ??? (eq. 27) p up 3 , v in q rr f s ?? = (eq. 28) p up 4 , r ds on () d i m n ----- - ?? ?? ?? 2 i pp 2 12 --------- - + ?? (eq. 29) isl6312a
27 fn9290.4 april 29, 2010 the total power dissipated by the upper mosfet at full load can now be approximated as the summation of the results from equations 26, 27, 28 and 29. since the power equations depend on mosfet parameters, choosing the correct mosfets can be an it erative process involving repetitive solutions to the loss equations for different mosfets and different switching frequencies. package power dissipation when choosing mosfets it is important to consider the amount of power being dissipat ed in the integrated drivers located in the controller. since there are a total of three drivers in the controller pack age, the total power dissipated by all three drivers must be less than the maximum allowable power dissipation for the qfn package. calculating the power dissipatio n in the drivers for a desired application is critical to ensure safe operation. exceeding the maximum allowable power dissipation level will push the ic beyond the maximum recommended operating junction temperature of 125 c. the maximum allowable ic power dissipation for the 7x7 qfn package is approximately 3.5w at room temperature. see ?layout considerations? on page 32 for thermal transfer improvement suggestions. when designing the isl6312a into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected mosfets. the total gate drive power losses, p qg_tot , due to the gate charge of mosfets an d the integrated driver?s internal circuitry and their corresponding average driver current can be estimated with equations 30 and 31, respectively. in equations 30 and 31, p qg_q1 is the total upper gate drive power loss and p qg_q2 is the total lower gate drive power loss; the gate charge (q g1 and q g2 ) is defined at the particular gate to source drive voltage pvcc in the corresponding mosfet data sheet; i q is the driver total quiescent current with no load at both drive outputs; n q1 and n q2 are the number of upper and lower mosfets per phase, respectively; n phase is the number of active phases. the i q* vcc product is the quiescent power of the controller without capacitive load and is typically 75mw at 300khz. the total gate drive power loss es are dissipated among the resistive components along the transition path and in the bootstrap diode. the portion of the total power dissipated in the controller itself is the power dissipated in the upper drive path resistance, p dr_up , the lower drive path resistance, p dr_up , and in the boot strap diode, p boot . the rest of the power will be dissipated by the external gate resistors (r g1 and r g2 ) and the internal gate resistors (r gi1 and r gi2 ) of the mosfets. figures 16 and 17 show the typical upper and lower gate drives turn-on transition path. the total power dissipation in the controller itself, p dr , can be roughly estimated as: p qg_tot p qg_q1 p qg_q2 i q vcc ? ++ = (eq. 30) p qg_q1 3 2 -- - q g1 pvcc f sw n q1 n phase ?? ??? = p qg_q2 q g2 pvcc f sw n q2 n phase ???? = i dr 3 2 -- - q g1 n ? q1 ? q g2 n q2 ? + ?? ?? n phase f sw i q + ?? = (eq. 31) figure 16. typical upper-gate drive turn-on path figure 17. typical lower-gate drive turn-on path q1 d s g r gi1 r g1 boot r hi1 c ds c gs c gd r lo1 phase pvcc ugate pvcc q2 d s g r gi2 r g2 r hi2 c ds c gs c gd r lo2 lgate p dr p dr_up p dr_low p boot i q vcc ? () +++ = (eq. 32) p dr_up r hi1 r hi1 r ext1 + -------------------------------------- r lo1 r lo1 r ext1 + ---------------------------------------- + ?? ?? ?? p qg_q1 3 --------------------- ? = p dr_low r hi2 r hi2 r ext2 + -------------------------------------- r lo2 r lo2 r ext2 + ---------------------------------------- + ?? ?? ?? p qg_q2 2 --------------------- ? = r ext1 r g1 r gi1 n q1 ------------- + = r ext2 r g2 r gi2 n q2 ------------- + = p boot p qg_q1 3 --------------------- = isl6312a
28 fn9290.4 april 29, 2010 inductor dcr curren t sensing component selection the isl6312a senses each i ndividual channel?s inductor current by detecting the voltage across the output inductor dcr of that channel (as describ ed in the ?continuous current sampling? on page 12). as figure 18 illustrates, an r-c network is required to accura tely sense the inductor dcr voltage and convert this informat ion into a current, which is proportional to the total output current. the time constant of this r-c network must match the time constant of the inductor l/dcr. the r-c network across the inductor also sets the overcurrent trip threshold for the regulator. before the r-c components can be selected, the desired overcurrent protection level should be chosen. the minimum overcurrent trip threshold the controller can support is dictated by the dcr of the inductors and the number of active channels. to calculate the minimum overcurrent trip level, i ocp,min , use equation 33, where n is the number of active channels, and dcr is the individual inductor?s dcr. if the desired overcurrent trip level is equal to or less then the minimum overcurrent trip level, follow the steps below to choose the component values for the r-c current sensing network : 1. choose an arbitrary value for c 1 . the recommended value is 0.1f. 2. plug the inductor l and dcr component values, and the value for c 1 chosen in step 1, into equation 34 to calculate the value for r 1 . 3. resistor r 2 should be left unpopulated. if the desired overcurrent trip level is greater then the minimum overcurrent trip level, i ocp,min , then a resistor divider r-c circuit should be used to set the desired trip level. follow the steps below to choose the component values for the resistor divider r-c current sensing network : 1. choose an arbitrary value for c 1 . the recommended value is 0.1f. 2. plug the inductor l and dcr component values, the value for c 1 chosen in step 1, the number of active channels n, and the desired ov ercurrent protection level i ocp into equations 35 and 36 to calculate the values for r 1 and r 2 . due to errors in the inductance or dcr it may be necessary to adjust the value of r 1 and r 2 to match the time constants correctly. the effects of time c onstant mismatch can be seen in the form of droop overshoot or undershoot during the initial load transient spike, as shown in figure 19. follow the steps below to ensure the r-c and inductor l/dcr time constants are matched accurately. 1. capture a transient event with the oscilloscope set to about l/dcr/2 (sec/div). for example, with l = 1h and dcr = 1m , set the oscilloscope to 500 s/div. 2. record v1 and v2 as shown in figure 19. 3. select new values, r 1,new and r 2,new , for the time constant resistors based on the original values, r 1,old and r 2,old , using equations 37 and 38. 4. replace r 1 and r 2 with the new values and check to see that the error is corrected. repeat the procedure if necessary. figure 18. dcr sensing configuration i n - + isen-(n) sample isl6312a internal circuit v in ugate(n) r isen dcr l inductor r 1 v out c out - + v c (s) c 1 i l - + v l (s) i sen r 2* v c (s) + - *r 2 is optional isen+(n) lgate(n) mosfet driver i ocp min , 0.0375 n ? dcr -------------------------- - = (eq. 33) r 1 l dcr c 1 ? ------------------------- = (eq. 34) i ocp i ocp min , r 1 li ocp ? c 1 0.0375 n ?? -------------------------------------- - = (eq. 35) i ocp i ocp min , > (eq. 36) r 2 li ocp ? c 1 i ocp dcr 0.0375 n ? ? ? () ? ---------------------------------------------------------------------------------- = r 1new , r 1old , v 1 v 2 ---------- ? = (eq. 37) r 2new , r 2old , v 1 v 2 ---------- ? = (eq. 38) isl6312a
29 fn9290.4 april 29, 2010 loadline regulation resistor for loadline regulation a copy of the internal average sense current flows out of the fb pin across the loadline regulation resistor, labeled r fb in figure 6. this resistor?s value sets the desired loadline required for the application. the desired loadline, r ll , can be calculated by the following equation where v droop is the desired droop voltage at the full load current i fl . based on the desired loadline, the loadline regulation resistor, r fb , can be calculated from equation 40 or equation 41, depending on the r- c current sense circuitry being employed. if a basic r-c sense circuit consisting of c 1 and r 1 is being used, use equation 40. if a resistor divider r-c sense circuit consisting of r 1 , r 2 , and c 1 is being used, use equation 41. in equations 40 and 41, r ll is the loadline resistance; n is the number of active channels; dcr is the dcr of the individual output inductors; and r 1 and r 2 are the current sense r-c resistors. iout pin resistor a copy of the average sense cu rrent flows out of the iout pin, and a resistor, r iout , placed from this pin to ground can be used to set the overcurrent protection trip level. based on the desired overcurrent trip threshold, i ocp , the iout pin resistor, r iout , can be calculated from equation 42 or equation 43, depending on the r- c current sense circuitry being employed. if a basic r-c sense circuit consisting of c 1 and r 1 is being used, use equation 42. if a resistor divider r-c sense circuit consisting of r 1 , r 2 , and c 1 is being used, use equation 43. compensation the two opposing goals of compensating the voltage regulator are stability and speed. the load-line regulated converter behaves in a similar manner to a peak current m ode controller because the two poles at the output filt er l-c resonant frequency split with the introduction of current informat ion into the control loop. the final location of th ese poles is determ ined by the system function, the gain of the current signal, and the value of the compensation components, r c and c c . since the system poles and zero are affected by the values of the components that are me ant to compensate them, the solution to the system equation becomes fairly complicated. fortunately, there is a simple approximation that comes very close to an optimal solution. treating the system as though it were a voltage-mode regulator, by compensating the l-c poles and the esr zero of the voltage mode approximation, yields a solution that is always stable with very close to ideal transient performance. select a target bandwidth for the compensated system, f 0 . the target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per-channel switching frequency. the values of the compensation components depend on the relationships of f 0 to the l-c pole frequency and the esr zero frequency. for each of the following three, there is a separate set of equations for the compensation components. figure 19. time constant mismatch behavior v 1 v out i tran v 2 i r ll v droop i fl ------------------------ - = (eq. 39) r fb r ll n 300 ?? dcr --------------------------------- - = (eq. 40) (eq. 41) r fb r ll n 300 r 1 r 2 + () ?? ? dcr r 2 ? ---------------------------------------------------------------- = (eq. 42) r iout 600 n ? dcr i ocp ? -------------------------------- = i ocp i ocp min , (eq. 43) r iout 600 n ? dcr i ocp ? -------------------------------- r 1 r 2 + r 2 -------------------- - ?? ?? ?? ? = i ocp i ocp min , > figure 20. compensation configuration for load-line regulated isl6312a circuit isl6312a comp c c r c r fb fb vdiff c 2 (optional) isl6312a
30 fn9290.4 april 29, 2010 in equation 44, l is the per-channel filter inductance divided by the number of active channels; c is the sum total of all output capacitors; esr is the equivalent series resistance of the bulk output filter capacitance; and v pp is the peak-to-peak sawtooth signal amplitude as described in the ?electrical specifications? on page 6. once selected, the compensation values in equation 44 assure a stable converter with reasonable transient performance. in most cases, transient performance can be improved by making adjustments to r c . slowly increase the value of r c while observing the transient performance on an oscilloscope until no further improvement is noted. normally, c c will not need adjustment. keep the value of c c from equation 44 unless some performance issue is noted. the optional capacitor c 2 , is sometimes needed to bypass noise away from the pwm comparator (see figure 20). keep a position available for c 2 , and be prepared to install a high frequency capacitor of between 22pf and 150pf in case any leading edge jitter problem is noted. output filter design the output inductors and the output capacitor bank together to form a low-pass filter re sponsible for smoothing the pulsating voltage at the phase nodes. the output filter also must provide the transient ene rgy until the regulator can respond. because it has a low bandwidth compared to the switching frequency, the outp ut filter limits the system transient response. the output capacitors must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. in high-speed converters, the out put capacitor bank is usually the most costly (and often the largest) part of the circuit. output filter design begins with minimizing the cost of this part of the circuit. the critical load parameters in choosing the output capacitors are the maximum size of the load step, i, the load-current slew rate, di/dt, and the maximum allowable output-voltage deviation under transient loading, v max . capacitors are characterized according to their capacitance, esr, and esl (equivalent series inductance). at the beginning of the load tr ansient, the output capacitors supply all of the transient cu rrent. the output voltage will initially deviate by an amount approximated by the voltage drop across the esl. as the load current increases, the voltage drop across the esr increases linearly until the load current reaches its final value. the capacitors selected must have sufficiently low esl and esr so that the total output- voltage deviation is less than the allowable maximum. neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount: the filter capacitor must have sufficiently low esl and esr so that v < v max . most capacitor solutions rely on a mixture of high frequency capacitors with relatively lo w capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. minimizing the esl of the high-frequency capacitors allows them to support the output voltage as the current increases. minimizing the esr of the bulk capacitors allows them to supply the increased current with less output voltage deviation. the esr of the bulk capacitors also creates the majority of the output-voltage ripple. as th e bulk capacitors sink and source the inductor ac ripple current (see ?interleaving? on page 10 and equation 2), a voltage develops across the bulk capacitor esr equal to i c,pp (esr). thus, once the output capacitors are selected, the maximum allowable ripple voltage, v pp(max) , determines the lower limit on the inductance. since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. the output inductors must be capable of assuming the entire load current before the output voltage decreases more than v max . this places an upper limit on inductance. equation 47 gives the upper limit on l for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. equation 48 1 2 lc ? ?? ------------------------------- -f 0 > r c r fb 2 f 0 v pp lc ? ?? ? ? 0.66 v in ? ------------------------------------------------------- - ? = c c 0.66 v in ? 2 v pp r fb f 0 ?? ? ? ---------------------------------------------------- = case 1: 1 2 lc ? ?? ------------------------------- - f 0 1 2 c esr ?? ? ------------------------------------- < r c r fb v pp 2 ? () ? 2 f 0 2 lc ??? 0.66 v in ? ---------------------------------------------------------------- - ? = c c 0.66 v in ? 2 ? () 2 f 0 2 v pp r fb lc ? ?? ? ? ------------------------------------------------------------------------------------- = case 2: (eq. 44) f 0 1 2 c esr ?? ? ------------------------------------- > r c r fb 2 f 0 v pp l ?? ? ? 0.66 v in esr ?? -------------------------------------------- - ? = c c 0.66 v in esr c ?? ? 2 v pp r fb f 0 l ?? ? ? ? ---------------------------------------------------------------- = case 3: vesl di dt ---- - ? esr i ? + (eq. 45) l esr v in nv ? out ? ?? ?? v out ? f s v in v pp max () ?? ------------------------------------------------------------------- - ? (eq. 46) isl6312a
31 fn9290.4 april 29, 2010 addresses the leading edge. normally, the trailing edge dictates the selection of l because duty cycles are usually less than 50%. nevertheless, both inequalities should be evaluated, and l should be selected based on the lower of the two results. in each equation, l is the per-channel inductance, c is the total output capacitance, and n is the number of active channels. switching frequency there are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper mosfet loss calculation. these effects are outlined in mosfets , and they establish the up per limit for the switching frequency. the lower limit is established by the requirement for fast transient response and small output-voltage ripple. choose the lowest switching frequency that allows the regulator to meet the transient-response requirements. switching frequency is determined by the selection of the frequency-setting resistor, r t . figure 21 and equation 49 are provided to assist in selecting the correct value for r t . input capacitor selection the input capacitors are responsible for sourcing the ac component of the input current flowing into the upper mosfets. their rms current capa city must be sufficient to handle the ac component of the current drawn by the upper mosfets which is related to duty cycle and the number of active phases. for a four-phase design, use figure 22 to determine the input-capacitor rms current requirement set by the duty cycle, maximum sustai ned output current (i o ), and the ratio of the peak-to-peak inductor current (i l,pp ) to i o . select a bulk capacitor with a ripple current rating which will minimize the total number of input capaci tors required to support the rms current calculated. the voltage rating of the capacitors should also be at least 1.25 times greater than the maximum input voltage. figures 23 and 24 provide the same input rms current information for three-phase and two-phase designs respectively. use the same approach for selecting the bulk capacitor type and number. low capacitance, high-frequency ceramic capacitors are needed in addition to the input bulk capacitors to suppress leading and falling edge voltage spikes. the spikes result from the high current slew rate produced by the upper mosfet turn on and off. select low esl ceramic capacitors and place one as close as possible to each upper mosfet drain to minimize board parasitics and maximize suppression. l 2ncv o ??? i () 2 --------------------------------- v max iesr ? () ? ? (eq. 47) l 1.25 nc ?? i () 2 ---------------------------- - v max i esr ? () ? v in v o ? ?? ?? ?? (eq. 48) r t 10 10.61 1.035 f s () log ? () ? [] = (eq. 49) figure 21. r t vs switching frequency switching frequency (hz) r t (k ) 10 100 1000 10 100 1k 10k input-capacitor current (i rms/ i o ) figure 22. normalized input-capacitor rms current vs duty cycle for 4-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v o/ v in ) 0.3 0.1 0 0.2 i l (p-p) = 0 i l (p-p) = 0.25 i o i l (p-p) = 0.5 i o i l (p-p) = 0.75 i o figure 23. normalized input-capacitor rms current for 3-phase converter duty cycle (v in/ v o ) 00.4 1.0 0.2 0.6 0.8 input-capacitor current (i rms/ i o ) 0.3 0.1 0 0.2 i l(p-p) = 0 i l(p-p) = 0.25 i o i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o isl6312a
32 fn9290.4 april 29, 2010 layout considerations mosfets switch very fast and efficiently. the speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, radiate noise into the circuit and lead to device overvoltage stress. careful component selection, layout, and placement minimizes these voltage spikes. consider, as an example, the turnoff transition of the upper pwm mosfet. prior to turnoff, the upper mosfet was carrying channel current. during the turnoff, current stops flowing in the upper mosfet and is picked up by the lower mosfet. any inductance in the switched current path generates a large voltage spike during the switching interval. careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. there are two sets of crit ical components in a dc/dc converter using a isl6312a controller. the power components are the most critical because they switch large amounts of energy. next are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling. the power components should be placed first, which include the mosfets, input and output capacitors, and the inductors. it is important to have a symmetrical layout for each power train, preferably with the controller located equidistant from each. symmetrical layout allows heat to be dissipated equally across all power trains. equidist ant placement of the controller to the first three power trains it controls through the integrated drivers helps keep the gate drive traces equally short, resulting in equal trace impedances and similar drive capability of all sets of mosfets. when placing the mosfets try to keep the source of the upper fets and the drain of the lower fets as close as thermally possible. input bulk capacitors should be placed close to the drain of the upper fets and the source of the lower fets. locate the output induct ors and output capacitors between the mosfets and the load. the high-frequency input and output decoupling capacitors (ceramic) should be placed as close as practicable to the decoupling target, making use of the shortest connection paths to any internal planes, such as vias to gnd next or on the capacitor solder pad. the critical small components include the bypass capacitors for vcc and pvcc, and many of the components surrounding the controller including the feedback network and current sense compone nts. locate the vcc/pvcc bypass capacitors as close to the isl6312a as possible. it is especially important to locate the components associated with the feedback circuit close to their respective controller pins, since they belong to a high-impedance circuit loop, sensitive to emi pick-up. a multi-layer printed circuit board is recommended. figure 25 shows the connections of the critical components for the converter. note that capacitors c xxin and c xxout could each represent numerous physical capacitors. dedicate one solid layer, usually the one underneath the component side of the board, for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the phase terminal to output inductors short. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase nodes. use the remaining printed circuit layers for small signal wiring. routing ugate, lgate, and phase traces great attention should be paid to routing the ugate, lgate, and phase traces since they drive the power train mosfets using short, high current pulses. it is important to size them as large and as short as possible to reduce their overall impedance and inductance. they s hould be sized to carry at least one ampere of current (0.02? to 0.05?). going between layers with vias should also be avoided, but if so, use two vias for interconnection when possible. extra care should be given to the lgate traces in particular since keeping their impedance and inductance low helps to significantly reduce the possibilit y of shoot-through. it is also important to route each channels ugate and phase traces in as close proximity as possible to reduce their inductances. figure 24. normalized input-capacitor rms current for 2-phase converter 0.3 0.1 0 0.2 input-capacitor current (i rms/ i o ) 00.4 1.0 0.2 0.6 0.8 duty cycle (v in/ v o ) i l(p-p) = 0 i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o isl6312a
33 fn9290.4 april 29, 2010 via connection to ground plane island on power plane layer island on circuit plane layer key figure 25. printed circuit board power planes and islands heavy trace on circuit plane layer c boot1 r 1 c 1 c 2 r ofs r fb c bin1 (c hfout ) c bout (cf1) (cf2) r t c ref locate close to ic locate near load; (minimize connection locate near switching transistors; (minimize connection path) (minimize connection path) vid4 vid5 pgood vid3 vid2 vid1 vcc isl6312a vid0 fs ofs ref en_ph4 pwm4 load vrsel en +12v gnd +12v pwm vcc boot ugate phase pvcc lgate gnd isl6612 +12v vid6 vid7 ss +5v isen4- isen4+ isen3- isen3+ isen2- isen2+ isen1- isen1+ ovpsel fb comp vsen rgnd vdiff drsel +12v phase1 ugate1 boot1 lgate1 +12v phase2 ugate2 boot2 lgate2 pvcc1_2 +12v phase3 ugate3 boot3 lgate3 pvcc3 r ss c boot2 c boot3 (cf2) c bin2 c bin3 c 1 r 1 c 1 r 1 c 1 r 1 c 1 r 1 path) c bin4 r en1 r en2 r dr iout r iout isl6312a
34 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9290.4 april 29, 2010 current sense component placement and trace routing one of the most critical aspe cts of the isl6312a regulator layout is the placement of the inductor dcr current sense components and traces. the r-c current sense components must be placed as close to their respective isen+ and isen- pins on the isl6312a as possible. the sense traces that connect the r-c sense components to each side of the output inductors should be routed on the bottom of the board, away from the noisy switching components located on the top of the board. these traces should be routed side by side, and they should be very thin traces. it?s important to route these traces as far away from any other noisy traces or planes as possible. these traces should pick up as little noise as possible. thermal management for maximum thermal performanc e in high current, high switching frequency applicatio ns, connecting the thermal gnd pad of the isl6312a to the ground plane with multiple vias is recommended. this heat spreading allows the part to achieve its full thermal potential. it is also recommended that the controller be placed in a direct path of airflow if possible to help thermally manage the part. isl6312a
35 fn9290.4 april 29, 2010 isl6312a package outline drawing l48.7x7 48 lead quad flat no-lead plastic package rev 4, 10/06 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 7.00 b a 7.00 (4x) 0.15 index area pin 1 top view pin #1 index area 44x 0.50 4x 5.5 48 37 4. 30 0 . 15 1 36 25 48x 0 . 40 0 . 1 4 m 0.10 c ab 13 24 bottom view 12 5 0 . 2 ref 0 . 00 min. 0 . 05 max. detail "x" c 0 . 90 0 . 1 base plane see detail "x" c c 0.08 seating plane c 0.10 side view typical recommended land pattern 6 6 ( 6 . 80 typ ) ( 4 . 30 ) ( 48x 0 . 60 ) ( 44x 0 . 5 ) ( 48x 0 . 23 ) 0.23 +0.07 / -0.05

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